Synthesis report

Andrew Vu

Computer Engineering · Purdue University · Class of 2029

West Lafayette, IN
WNS: 0.00ns — MET

Andrew_Vu_Resume.pdf

Full synthesis report — updated March 2026

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1. Design summary // education

ParameterValue
InstitutionPurdue University, West Lafayette, IN
DegreeB.S. Computer Engineering
Expected tape-outMay 2029
GPA4.00 / 4.00
Target frequencyASIC / RTL design / chip design

2. Area utilization // skills & evidence

DomainDemonstrated byTools
RTL designrisc_v_core, booth_mult, cache, uartSystemVerilog, Verilog
Computer arch5-stage pipeline, hazard/forwarding, branch prediction, cache hierarchyOnline Resources
Verificationcocotb testbenches for SoC modules, Verilator simulationscocotb, Verilator
STA / synthesisTiming closure on risc_v_core, cacheLibreLane toolchain
PCB designaudio_visualizer, armor_plate, fluo_chargerEasyEDA, Altium
FPGAPrototyping & validation of RTL designsIntel Quartus
SoftwareEDA scripting, embedded firmware, build toolingC/C++, Python

3. Timing report // experience timeline

Purdue SoCET — GPU hardware teamAug 2026 — present

Contributing to GPU compute unit RTL and microarchitecture exploration.

SystemVerilogGPU archRTL design
Purdue RobomasterAug 2025 — present

Electrical/PCB team. Designed armor plate, fluorescent charger, and audio visualizer boards.

EasyEDAPCB designSoldering
EPICS Harnessing Data Revolution (HDR)Aug 2025 — present

Contributing to full-stack web application for Standing Rock Tribal environmental data collection.

Higher EducationData Collection
Purdue IEEE MTT-SSep 2025 — Feb 2026

Technical team member of the Microwave Theory and Technology Society student chapter.

Altium DesignerRF Circuits
PTSC M&C — VietnamJul 2024 — Aug 2024

Engineering intern. Technical documentation, weekly progress reports, daily construction metrics logging.

DocumentationData loggingExcel
SEAGLE Project — Head of Technical DepartmentNov 2022 — Oct 2024

4. Design instances // key projects

ModuleDescriptionTypeStatus
risc_v_core5-stage pipelined RV32IMSoCsynthesized
booth_multRadix-4 Encoding Wallace treeSoCsynthesized
cache4-bank direct-mappedSoCsynthesized
uart8-bit TX/RXSoCsynthesized
audio_visualizerLED audio display driverPCBfab + soldered
armor_plate_v1Rechargeable armor systemPCBPCB complete
fluo_chargerFluorescent projectile chargerPCBPCB complete

Full details at andrewvu.netlify.app/projects