vu89@purdue.edu
clk en

module andrew_vu #(parameter BIRTHDATE = 03_02_2007)

Andrew Vu

Computer Engineering @ Purdue ’29.
Designing silicon, one flip-flop at a time.

Andrew Vu
DIE_PHOTO
.status(seeking_opportunities)   .focus(RTL_design, computer_architecture)
.tools(SystemVerilog/Verilog, Verilator, cocotb, Librelane toolchain)   .also(Python, C/C++)

// system architecture — hover to explore

SoC domain Standalone EX IF / MEM bus APB risc_v_core 5-stage pipelined RV32IM booth_mult Radix-4 cache 4-bank direct-mapped bus interconnect uart 8-bit TX/RX // syntax error: module not found // WNS: -0.42ns timing not met // elaboration pending...
Hover an IP block to see details

// SKILL_REG[31:0] — capability register

RTL_DESIGN [31:22] 10b COMP_ARCH [21:15] 7b VERIF [14:9] 6b STA_SYNTH [8:3] 6b SW [2:0]
Hover a bitfield — wider fields = deeper expertise

// $display — simulation log

2026-03-17 andrewvu.netlify.app goes live — first synthesis run complete milestone

// waveform dump — contribution activity

Andrew Vu's GitHub contribution graph

Live from GitHub · click to view profile

// mailbox #(msg) — inter-process communication

I read every message. Drop me a line and I'll get back to you soon.

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