// SM_0: get_to_know(andrew, thread_id) — 4 threads, 1 warp

SM0 — warp #0 4/4 active

// T0 — REG_FILE[0] output:

Born and raised in Vietnam. Moved to the US for college. I chose Purdue because it's a good engineering school, not because I knew what I wanted to do. However, I never regret my choice. Also, when I first learned about the tip culture in the US, I've never eaten out ever since the first semester.

PC:

0x00 / 0x03

// pipeline flush — switching execution context to datasheet mode

Datasheet

AV-2029A

First-year human compute unit, ASIC/RTL specialization, GPU-curious

active

1. Features

- Native SystemVerilog / Verilog processing pipeline

- Integrated RISC-V SoC design experience

- Verification engine: cocotb, Verilator, OpenSTA, LibreLane toolchain

- FPGA prototyping interface (Altera Cyclone)

- GPU architecture and ML/AI hardware accelerator interest bus

- Board-level PCB design interface (EasyEDA, Altium)

- Software compatibility layer: C/C++, Python

2. Functional description

The AV-2029A is a first-year computer engineering unit at Purdue University, optimized for digital ASIC design with a growing focus on processor microarchitecture and GPU compute. The core pipeline already supports RTL design in SystemVerilog from specification through verification and synthesis, with an integrated RISC-V SoC as the flagship design. An on-chip verification subsystem drives pre-silicon validation through cocotb, Verilator, and the full LibreLane open-source EDA stack.

Currently ramping up a GPU hardware design track through Purdue SoCET, with long-term target of chip design at an ASIC company. When not at the EDA workstation, found either doomscrolling or bouldering.

3. Absolute maximum ratings Exceeding these may cause permanent damage

Parameter	Symbol	Rating	Unit
Concurrent deadline pressure	P_DL	4	projects
Maximum sustained focus	T_FOCUS	10	hours
Supply voltage (caffeine)	V_CC	100	mg / day
Minimum sleep cycle	T_SLEEP	5	hours
Debug session endurance	T_DBG	6	hours continuous

5. Auxiliary I/O Active peripheral interfaces

Interface	Description	Status	Spec
CLIMB_IF	Bouldering — vertical problem-solving with no safety net	active	V6
AUDIO_DAC	Audiophile subsystem — 7Hz Timeless · Moondrop Blessing 3 · FLAC · foobar2000	active	IEM x2
RUN_CLK	5km training loop — chasing sub-20:00 timing closure	WIP	~21:xx
CAFF_PLL	Power recovery — 20min nap or 100mg caffeine pill (Monster not in budget)	frequent	PRN
GACHA_EN	Gacha addiction bus — dopamine-locked to the pull animation	critical	$$$
DEFER_EN	Procrastination engine — always enabled, no disable pin	stuck high	1b

6. Known errata Will be addressed in future silicon revisions

ID	Description	Severity	Workaround
ERR001	Trying to learn everything just to get burned out	critical	rest
ERR002	DEFER_EN line stuck high — root cause unknown, persists across all silicon revisions	major	deadline
ERR003	Not beating the “engineers don’t shower” allegations	major	soap

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